The present invention relates to a process for manufacturing a magnetic bubble memory chip, and more particularly, to a process for manufacturing a dual spacing type magnetic bubble memory chip having a thin bubble film, on which a first area is provided with minor loop transmission lines for memorizing bubble information and a second area is provided with major transmission lines for recording or reading out the bubble information with respect to the minor loop transmission lines.
Recent developments in the design of magnetic bubble memory chips has led to a demand that the bubble information accommodating sections of these chips, comprising the minor loop transmission lines, be made more and more compact to enable a higher density installation of these devices. For instance, in a 4 megabit chip the pattern periods should be 4 .mu.m. On the other hand, in the function sections, such as swap gates, replicate gates, and generators, and major transmission lines (major lines) for recording or reading out the bubble information accommodated in the minor loop transmission line organization, relatively large patterns, such as 16 .mu.m periods, are used to enable a higher degree of positioning accuracy during the manufacturing process of the bubble memory chip. However, where different size transmission patterns are used in a single memory chip, as mentioned above, it has been found that problems concerning the characteristics will occur due to differences in the driving forces.
FIG. 1 illustrates a cross-section of a magnetic bubble memory chip having a dual spacing layer structure manufactured in accordance with a prior art technique, and FIG. 2 illustrates an enlarged cross-section of the bubble memory chip of FIG. 1 during the manufacturing process. According to the known art, a layer of SiO.sub.2 2 is formed on a garnet film 1 by sputtering and gold (Au) conductive patterns 3 for controlling function gates are formed thereon. In order to level the steps of the conductive pattern 3, a high temperature tolerant resin 4, such as polyladder-organosiloxane (PLOS), is coated thereon and thermoset, and then only the PLOS layer 4 in an area 5 of the chip corresponding to the small-sized transmission patterns for the information accommodating section is etched, with a plasma etching agent including CF.sub.4 etchant gas. The permalloy patterns 6 for the transmission patterns are formed thereafter.
The above-mentioned prior art method has several problems. A first is the unevenness of the rate of etching in each batch when manufacturing the magnetic bubble memory chips. Conventionally, a planner plate type etching machine is generally used for etching such a high temperature tolerant resin 4, and although this type of etching machine is superior to a cylindrical type etching machine in etching evenness, usually there is still a variation in the rate of etching of within .+-.5% per batch. For instance, if the film thickness of the high temperature tolerant resin layer 4 is 3800 .ANG. and the thickness is to be reduced by etching by 3000 .ANG., to obtain a spacer having a thickness of 1300 .ANG. including the SiO.sub.2 layer 2 of 500 .ANG., a variation of etching within .+-.150 .ANG. will occur per batch when the thickness of the high temperature tolerant resin is reduced by 3000 .ANG.. In addition, when variation between the batches are taken into account, there may be a variation of at least .+-.300 .ANG.. Such a large variation of .+-.300 .ANG. will cause a serious problem, i.e., degradation of performance of the bubble memory chip, since 1300 .ANG. is the most favorable thickness for a spacer, as will be described hereinafter.
A second problem is that when an uneven face 7 having a thickness of 200 .ANG. to 300 .ANG. is formed on the etched surface, as seen from FIG. 2, the permalloy film formed thereon may have a local high spot Hc, which will affect the characteristics of the bubble memory.